1. Field
Embodiments of the invention relate to the field of system clock architectures. More particularly, embodiments of the invention relate to synchronizing and aligning differing clock domains.
2. Description of Related Art
As computer devices and systems continue to advance and become more complex, effective and efficient techniques for transferring data between various components in computer systems have become more and more critical in computer system design and implementation. In particular, techniques to increase data transfer rates between input/output (I/O) devices (e.g. often controlled through an I/O control hub) and system memory (e.g. often controlled through a memory control hub) are continuously under examination in order to improve the overall performance of computer systems.
This is particularly true for the personal computer industry. For example, in today's competitive marketplace for personal computers, computer speed for the rendering of graphics has become one of the key consumer considerations in purchasing a new personal computer. The speed of a personal computer in rendering graphics has a direct impact on the performance of the main functions that a typical computer user wishes to utilize their computer for, such as: games, Internet surfing, application software programs, and a myriad of other computer uses most all of which depend on the speedy rendering of graphics.
Many of today's computer systems include a processor coupled to a memory controller hub (MCH) by a front-side bus (FSB) wherein system memory is coupled to the MCH. Further, I/O devices are coupled through an I/O control hub (ICH) to the MCH by a back-side bus (BSB). The computer's speed and performance, especially for the rendering of graphics, is often tied to the rate of data transfer between the processor and the MCH along the FSB and between the system memory of the MCH and I/O devices along the BSB. The rate of data transfer along the front-side bus is based upon the clock speed (e.g. measured in MHz) of the front-side bus, which is calibrated by a FSB clock signal. Similarly, the rate of data transfer along the backside bus is based upon the clock speed (e.g. measured in MHz) of the back-side bus, which is calibrated by a BSB clock signal. Unfortunately, typically, the clock speeds for the transfer of data along the front-side bus and back-side bus are not synchronized and/or aligned resulting in serious inefficiencies.